A transmission apparatus that multiplexes low-speed signals to transmit the signals in the form of a high-speed frame has been known. FIG. 9 is a diagram illustrating one example of a transmission apparatus 100 of related art. As illustrated in FIG. 9, the transmission apparatus 100 of the related art includes data processing units 110, a multiplexer (MUX) 120, memories 130 (e.g., first-in first-out (FIFO) memories), and phase comparators 140. As illustrated in FIG. 9, the transmission apparatus 100 further includes an overhead (OH) rewriting unit 150 and an OH processing unit 160.
For example, as illustrated in FIG. 9, the transmission apparatus 100 uses the MUX 120 to multiplex the reception data transferred at four different low-speed transfer rates for Ch. (channel) 1 to Ch. 4. As illustrated in FIG. 9, each data processing unit 110 has an OH-data detecting unit 111, a memory 112 (e.g., a FIFO memory), and an OH-data inserting unit 113.
The OH-data detecting unit 111 detects OH data, which is control data contained in the reception data. The memory 112 stores data (hereinafter referred to as “data”) other than the OH data contained in the reception data. The OH-data inserting unit 113 inserts OH data read by the OH processing 160 (described below) into the data stored by the memory 112, to thereby generate transmission data. The OH-data inserting unit 113 sends the transmission data to the MUX 120 in synchronization with the phase of a reference clock (Ref CLK) for the transmission data.
The MUX 120 multiplexes the transmission data sent from the Ch. 1 to Ch. 4 data processing units 110 to generate MUX data and sends the MUX data in synchronization with the phase of the Ref CLK. The memories 130 store the OH data recorded by the OH processing unit 160. Each phase comparator 140 outputs a phase difference between a LINE CLK and a Read CLK. The LINE CLK serves as a reference clock for the reception data.
By using the phase difference output from the phase comparator 140 and the Read CLK (which serves as a reference clock for reading the OH data), the OH rewriting unit 150 reads the OH data from the memory (FIFO) 130 and rewrites the read OH data so that OH data indicates an apparatus-setting value or the like. For example, when a failure occurs in a network to which the transmission apparatus 100 belongs, the OH rewriting unit 150 rewrites part of the OH data so that it indicates information of a failed portion or the like.
By using the phase difference output from the phase comparator 140 and the phase of the LINE CLK, the OH processing unit 160 records the OH data detected by the OH-data detecting unit 111 to the corresponding memory 130. The OH processing unit 160 sends the OH data, subjected to the rewriting processing by the OH rewriting unit 150, to the OH-data inserting unit 113 in synchronization with the phase of the Ref CLK.
Thus, the transmission apparatus 100 controls the timings of the recording and reading of the OH data by using the phase difference between the LINE CLK and the Read CLK, to thereby prevent misreading of the OH data recorded in the memories 130. The transmission apparatus 100 asynchronously executes processing on the reception data by using the memories 130, the phase comparators 140, and the Read CLKs corresponding to the respective Ch. 1 to Ch. 4.
Examples of the related art include Japanese Unexamined Patent Application Publication Nos. 8-298494 and 2008-131063.
In the related art, however, there is a problem in that the circuit scale increases. More specifically, in a case in which processing such as rewriting or insertion is to be executed on the OH data, the transmission apparatus 100 of the related art needs to have the phase comparators 140 and the Read CLKs for the respective channels. As a result, there is a problem in that the circuit scale of the transmission apparatus increases.
Accordingly, in view of the above-described problem of the related art, a technology disclosed herein is aimed to provide a control-data processing program, a control-data processing method, and a transmission apparatus which can reduce the circuit scale.